Design and Implementation of Voltage-Mode MIN/MAX Circuits

In this paper, a general architecture for analog implementation of MIN/MAX and other rank order circuits is presented. Based on general architecture, proposed MIN/MAX circuits are implemented. The proposed circuits are composed of a differential amplifier with merged n-inputs and a MCSAL circuit to choose the desired input. The advantages of the proposed structure are simplicity, very high resolution, very low supply voltage requirements, very low output resistor, low power dissipation, low active area and simple expansion for multiple inputs by adding only three transistors for each extra input. The post-layout simulation results of proposed circuits are presented by HSPICE software in 0.35-μm CMOS process technology. The total power dissipation of proposed circuits is about 110-μW. Also, the total active area is about 550-μm2 for five-input proposed circuits, and would be negligibly increased for each extra input.